1. Field of the Invention
This invention relates to a power semiconductor device having a MOSFET structure inserted between a cathode emitter and a cathode electrode.
2. Description of the Related Art
A turn-off thyristor shown in FIG. 31 that effects turn-off control by means of an insulated gate has been disclosed in B. J. Baliga, "The MOS-Gated Emitter Switched Thyristor," IEEE ELECTRON DEVICE LETTERS, Vol. 11, pp. 75-77, 1990. In this structure, an n-base layer 52 is formed in contact with a p-emitter layer 51. In the n-base layer 52, a p-base layer 53 and an n-emitter layer 54 are formed by diffusion in sequence, thus forming a pnpn thyristor structure. An anode electrode 56 is in contact with the p-emitter layer 51 by a low resistance. An n-source layer 55 is formed near the n-emitter layer 54. At the surface of the p-base layer 53 sandwiched by these two layers, a gate electrode 59 is formed via a gate insulating film 58. Further, a cathode electrode 57 is in contact with both the n-source layer 55 and a p+-layer 64.
A method of manufacturing the aforesaid device is as follows. First, as shown in FIG. 32A, p-type impurity ions are implanted into the bottom surface of an n-type semiconductor substrate and then diffused to form the p-emitter layer 51. Further, p-type impurity ions are selectively implanted into the top surface of the substrate and then diffused to form the p-base layer 53. Then, as shown in FIG. 32B, p-type impurity ions are selectively implanted into the surface of the p-base layer 53 and then diffused to form the p.sup.+ -layer 64.
Next, as shown in FIG. 32C, the gate oxide film 58 is formed on the top surface of the wafer that has undergone the above processes. Further on the gate oxide film, a material (e.g., polysilicon) for the gate electrode 59 is deposited. After the deposition, the gate electrode material and the gate oxide film are patterned, and n-type impurity ions are implanted into the resulting opening portions and then diffused to form the n-emitter layer 54 and the n-source layer 55. After that, as shown in FIG. 32D, the interlayer insulating film 63 is deposited and a contact hole 65 is formed. Then, the cathode electrode 57 is connected to the contact hole 65, and the anode electrode 56 is connected to the p-emitter layer 51.
The operation of the above device is as follows. When a positive voltage is applied to the gate electrode 59, electrons pass through the cathode electrode 57, the n-source layer 55, and the n-channel region CH.sub.1 and arrive at the n-emitter layer 54. In this state, when a base current is supplied, electrons are injected from the n-emitter layer 54, thereby turning on the thyristor structure consisting of the p-emitter layer 51, the n-base layer 52, the p-base layer 53, and the n-emitter layer 54. Namely, the structure of this device is constructed such that a MOSFET is connected in series with a thyristor structure.
When a negative voltage is applied to the gate electrode 59, the channel region CH.sub.1 becomes nonconductive, which stops the supply of electrons to the n-emitter layer 54, causing the thyristor to turn off. At this time, the holes accumulated inside are discharged to the cathode electrode 57 through the p.sup.+ -layer 64.
Such a conventional insulated-gate turn-off thyristor structure has a disadvantage in that the injection efficiency of electrons from the n-emitter layer 54 into the p-base layer 53 is low, since the p+-layer 64 formed in the p-base layer 53 is in contact with the cathode electrode 57 by a low resistance. In addition, because holes pass through the p-base layer 53 and p.sup.+ -layer 64 directly under the n-source layer 55 and are discharged to the cathode electrode 57, the p-n junction is forward-biased by a voltage drop caused by the p-layers 53 and 64. This causes a problem in that a parasitic thyristor consisting of the p-emitter layer 51, n-base layer 52, p-base layer 53, and n-source layer 55 latches up, preventing the device from turning off.
To make it difficult for the parasitic thyristor to latch up, it can be considered that the p.sup.+ -layer 64 is formed so as to completely cover the bottom of the n-source layer 55 with conventional ion implantation and diffusion techniques, however, the p.sup.+ -layer 64 reaches the channel region CH.sub.1. This shifts the impurity concentration of CH.sub.1 from its optimum value, making it difficult to control CH.sub.1 by the gate voltage. Further, to embed the p.sup.+ -layer 64 can be considered as a method of preventing the layer 64 from reaching CH.sub.1 during its formation. To achieve this, however, epitaxial growth techniques are required, which makes the processing complicated.
As mentioned above, with a conventional EST (emitter switched thyristor), it is difficult to meet the characteristics required for power semiconductor devices in terms of the turn-on and turn-off characteristics.
Additionally, in an insulated-gate turn-off thyristor formed by a conventional manufacturing method, because the p-base layer is short-circuited with the cathode electrode, the electron injection efficiency is low, preventing the production of much finer devices. There is another problem in that, because holes pass through the p-base layer directly under the n-source layer, this permits the parasitic thyristor to latch up, thus preventing the device from turning off. An attempt to overcome this problem requires epitaxial growth techniques in the manufacturing processes, consequently making these processes more complicated.